A brand new technical paper titled “Design-for-Take a look at Options for 3D Built-in Circuits” was printed by researchers at Duke College, Arizona State College, and NVIDIA.
Summary:
“As Moore’s Legislation approaches its limits, 3D built-in circuits (ICs) have emerged as promising alternate options to traditional scaling methodologies. Nonetheless, the advantages of 3D integration when it comes to decrease energy consumption, larger efficiency, and decreased space are accompanied by testing challenges. The distinctive vertical stacking of elements in 3D ICs introduces issues associated to the robustness of bonding surfaces. Furthermore, immature manufacturing processes throughout 3D fabrication can result in excessive defect charges in several tiers. Due to this fact, there’s a want for design-for-test options to make sure the reliability and efficiency of 3D-integrated architectures. On this paper, we offer a complete survey of current testing methods for 3D ICs. We describe latest advances, together with analysis efforts and trade observe, that tackle issues associated to bonding defects, elevated energy provide noise, fault prognosis, and fault localization particular to the distinctive traits of 3D ICs.”
Discover the technical paper right here. Printed June 2024.
S. -C. Hung, P. Bhoumik, A. Chaudhuri, S. Banerjee and Okay. Chakrabarty, “Design-for-Take a look at Options for 3D Built-in Circuits*,” in Built-in Circuits and Methods, doi: 10.23919/ICS.2024.3419629.
